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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
Memory Organization
The SST25WF512/010/020/040 SuperFlash memory arrays are organized in uniform 4 KByte with 16
KByte, 32 KByte, and 64 KByte (2 Mbit and 4 Mbit Only) overlay erasable blocks.
Device Operation
The SST25WF512/010/020/040 are accessed through the SPI (Serial Peripheral Interface) bus com-
patible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the
device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK).
The SST25WF512/010/020/040 support both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations.
The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the
bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising
edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the
SCK clock signal.
CE#
MODE 3
MODE 3
SCK
SI
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON T CAR E
MODE 0
SO
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1328 F03.0
Figure 3: SPI Protocol
?2011 Silicon Storage Technology, Inc.
5
DS25016A
06/11
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